1. Field of the Invention
The present invention relates to methods for fabricating an integrated circuit (IC). More particularly, present invention relates to methods for fabricating a non-volatile memory.
2. Description of Related Art
A non-volatile memory is characterized by maintaining stored data even when the power is off, and thus has become a mandatory device in many electronic products for providing normal operation when the electronic products are booted. Recently, the non-volatile memory has been widely adopted in personal computers (PCs) and other electronic equipment.
FIG. 1 is a schematic cross-sectional view of a conventional non-volatile memory. Referring to FIG. 1, the non-volatile memory includes a substrate 100, a source region 102a and a drain region 102b disposed in the substrate 100, and a gate stacked structure 112. The gate stacked structure 112 is constituted by a silicon oxide layer 104, a silicon nitride layer 106, another silicon oxide layer 108, and a gate 110 all having a uniform thickness. In the conventional non-volatile memory, one bit is respectively stored in the silicon nitride layer 106 around the source region 102a and the drain region 102b, such that a two-bit/cell memory is formed.
However, when programming the conventional two-bit/cell non-volatile memory, the two bits in the same memory cell are mutually affected. If one bit has been stored in a part near the drain region in the conventional non-volatile memory, a second-bit effect occurs when a reading operation is performed, such that a voltage in the portion where a high current is expected may drop. In other words, when the memory cell is being read, the existing bit poses a direct impact on the memory cell, thus increasing a barrier and a threshold voltage (Vt) for reading.
In view of the above, the second-bit effect not only substantially implicates the operation of devices, but also reduces the device reliability. Moreover, because the second-bit effect reduces a sense margin and a Vt window for operating the left bit and the right bit, thus an operation of multi-level cell memory is more difficult.
One of the current solutions is directed to increasing a drain voltage (Vd) for enhancing a drain-induced barrier lowering (DIBL), and thereby the increased barrier and the increased Vt arisen from the second-bit effect can be decreased. Nevertheless, since a dimension of the device is continuously shrinking, an excessive drain voltage will result in the operation difficulties as well.